Texas Instruments Recruitment 2022 | Physical Design Engineer | BE/ B.Tech – CSE/ IT/ ECE/ EEE | Bangalore
Company: Texas Instruments (India) Pvt Ltd
Texas Instruments Recruitment 2022: Texas Instruments Inc. (TI) is an American technology company that designs and manufactures semiconductors, which it sells to electronics designers and manufacturers globally. Headquartered in Dallas, Texas, United States, TI is one of the top ten semiconductor companies worldwide, based on sales volume. Texas Instruments’s focus is on developing analog chips and embedded processors, which accounts for more than 85% of their revenue.
TI also produces TI digital light processing (DLP) technology and education technology products including calculators, microcontrollers and multi-core processors. To date, TI has more than 43,000 patents worldwide
Company Website: www.ti.com
Positions: Physical Design Engineer
Experience: 1-5 years
Salary: Best in Industry
Job Location: Bangalore
Eligibility Criteria for Texas Instruments Recruitment 2022:
- Bachelors degree in Electrical Engineering, Electronics Technology, Electrical Engineering Technology, Electrical and Computer Engineering or related field
- Cumulative 3.0/4.0 GPA or higher
- >1-5 years’ experience in physical design
- Master’s / Bachelor’s / Diploma in Electronics/Electrical/Computer-Science
You would be Interacting closely with digital/analog designers and completely owning area-power-timing optimization, design closure and signoff of signal chain IPs and top level of Ethernet PHYs targeted at Automotive and Industrial markets. These designs and IPs (0.5 Million to 5 million gates; 100MHz – 2.5GHz ; 65nm/28nm CMOS) and are part of TI’s growing portfolio of IEEE compliant robust, low-power Ethernet PHYs with deterministic low latency and industry leading PTP/AVB/MACSEC for the industrial and automotive markets (including advanced single pair and multi-gigabit standards). The role provides excellent challenges and opportunities to innovate and grow within and beyond the core domain through functional rotations within the Ethernet product team.
Synthesis, DFT insertion, LEC
Place & Route
- Floor planning, power grid creation for sea-of-gate designs w/ memories
- Static and Dynamic IR drop analysis and optimization
- Resolving routing congestions and DRCs
- LVS closure
- Crosstalk analysis
- Good understanding of STA concepts, SDC constructs, design margins.
- Clock Tree Synthesis; Constraints to guide the CTS tool; Debugging
- Creation and review of Timing Constraints (jointly with RTL designers)
- Multi-Mode * Multi-Corner Timing Closure
- Manual analysis/debug of CTS and STA issues
- Metal-only ECOs (for functionality and timing)
- Tool Scripting for sanity checks, reporting, debug and automation
- Ability to root cause timing and clock issues (eg. constraints, structural aspects)
How to Apply for Texas Instruments Recruitment 2022?
Desirous candidates may apply through online mode.
Apply Link: Click Here